With the progress of transistor process technology, the dimension of transistors has shrunk and therefore the number of transistors per unit area of an integrated circuit has increased accordingly. The increased device density demands higher interconnect technology that can achieve signal transport between devices with a desired speed and satisfy low resistance and low capacitance (e.g., low RC time constant) requirements. The effect of interconnect RC time constant on signal delay is exacerbated as integrated circuits become more complex and feature sizes decreases. In semiconductor back-end-of line (BEOL) processing, metal interconnect structures are fabricated with inter-metal dielectric (IMD) layers, which can contribute capacitance to the metal interconnect structures. The capacitance contribution can undesirably reduce signal transport speed of the semiconductor circuitry.
The use of low dielectric constant (low-k) dielectric material to form the IMD layers has to some extent reduced the capacitance contribution and improved signal transport speed. However, the low-k dielectric material has disadvantageous features and properties such as high porosity, which make it susceptible to damage during certain semiconductor processes such as etching, deposition, and wet processes, which can degrade (increase) their dielectric constants.
Solutions are required that can achieve a desired capacitance, yield, and reliability, particularly at advanced technologies, for example, the 5-nanaometer node (N5) and beyond.